IEVC2024 | Special Session: Industry Forum

Invited Talks   Registration

Special Session: Industry Forum with APSIPA Industry Relations and Development, IEEE Signal Processing Society, IEEE Circuits and Systems Society, IEEE Solid-State Circuits Society

Theme: AI and the Era of Smart Semiconductors

Program

Invited Talks

Invited talk: SoC VLSI Physical Layouts and EDA Solutions to Enable Single-Digit Nanometer Semiconductor Volume Production for the Upcoming Artificial Intelligence

Abstract: The continuous win-win collaborations among university scientists, circuit design houses, semiconductor chip manufacturers and EDA companies in the past decades will continue since world-wide semiconductor experts are postulating that the complexities of the upcoming high-end electronic systems and cloud and data center chip sets with generative artificial intelligence capabilities will soon be in the range of multiple trillion transistors. Majority of the transistors in the advanced systems are categorized as advanced nanometer CMOS transistors, such as FinFET and GAA/nanosheet. SoC VLSI physical layout innovations and EDA solutions in FinFET, nanosheet. and 3DIC alliance are believed to be essential to achieve the trillion-transistor trend within a few years. The leap from traditional SoC/IC designs to 3DFabric (3DIC) designs will bring new benefits and opportunities that come out of the legacy silicon CMOS. Furthermore, this new paradigm inevitably demands new solutions on system design, verification, thermal management, mechanical stress, and electrical-photonic compliance of the entire 3DIC assembly and reliability.

Speaker: Prof. Keh-Jeng Chang

Deputy Director, Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan

Keh-Jeng Chang received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, and the Ph.D. degree in computer science from the University of California at Los Angeles, USA. After receiving his degree from UCLA, he spent more than 14 years conducting VLSI electronic design automation (EDA) researches in Silicon Valley in Northern California for two companies consecutively, i.e., Hewlett-Packard Company and Sequence Design Inc. Then, he returned to his home country Taiwan and continued his VLSI EDA researches at National Tsing Hua University and Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan. He has published scores of journal articles and conference papers and has been awarded more than 20 US patents, on methods and systems for yield improvement of nanometer CMOS and 3DIC.

IEEE CASS Tainan Chapter, Distinguished Lecture: Designing a Hardware Solution for Deep Neural Network Training

Abstract: The size and complexity of recent deep learning models continue to increase exponentially, causing a serious amount of hardware overheads for training those models. Contrary to inference-only hardware, neural network training is very sensitive to computation errors; hence, training processors must support high-precision computation to avoid a large performance drop, severely limiting their processing efficiency. This talk will introduce a comprehensive design approach to arrive at an optimal training processor design. More specifically, the talk will discuss how we should make important design decisions for training processors in more depth, including i) hardware-friendly training algorithms, ii) optimal data formats, and iii) processor architecture for high precision and utilization.

Speaker: Prof. Dongsuk Jeon

Seoul National University, Korea

Dongsuk Jeon received a B.S. degree in electrical engineering from Seoul National University, Seoul, South Korea, in 2009 and a Ph.D. degree in electrical engineering from the University of Michigan, Ann Arbor, MI, USA, in 2014. From 2014 to 2015, he was a Post-doctoral Associate with the Massachusetts Institute of Technology, Cambridge, MA, USA. He is currently an Associate Professor with the Graduate School of Convergence Science and Technology, Seoul National University. His current research interests include hardware-oriented machine learning algorithms, hardware accelerators, and low-power circuits.
Dr. Jeon was a recipient of the Samsung Scholarship for Graduate Studies in 2009, the Samsung Humantech Thesis Contest Gold Award in 2021, and the Best Design Award at International Symposium on Low Power Electronics and Design (ISLPED) in 2021. He has served for the Technical Program Committee of the ACM/IEEE Design Automation Conference and IEEE/ACM Asia and South Pacific Design Automation Conference. He is now serving as a Distinguished Lecturer of the IEEE Solid-State Circuits Society and an Associate Editor of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Invited Talk: MediaGnosis: Towards Building Multimodal Foundation Model

Abstract: This industry seminar introduces NTT’s multi-modal processing AI, MediaGnosis. MediaGnosis provides the all-in-one cross-media processing module for visual, audio, and text media. One of the most notable distinctions of MediaGnosis has a human-like cross-media processing architecture. We will describe the motivation behind this architecture, some of the many novel algorithms for media processing in MediaGnosis, and the integrated method of each media processing.

Speaker:Dr. Ryo Masumura

NTT Corporation, Japan

Ryo Masumura received B.E., M.E., and Ph.D. degrees in engineering from Tohoku University, Sendai, Japan, in 2009, 2011, 2016, respectively. Since joining Nippon Telegraph and Telephone Corporation (NTT) in 2011, he has been engaged in research on speech recognition, spoken language processing, and natural language processing. He received the Student Award and the Awaya Kiyoshi Science Promotion Award from the Acoustic Society of Japan (ASJ) in 2011 and 2013, respectively, the Sendai Section Student Awards The Best Paper Prize from the Institute of Electrical and Electronics Engineers (IEEE) in 2011, the Yamashita SIG Research Award and the SIG-NL Excellent paper award from the Information Processing Society of Japan (IPSJ) in 2014 and 2018, the Young Researcher Award and the Paper Award from the Association for Natural Language Processing (NLP) in 2015 and 2020, the ISS Young Researcher’s Award in Speech Field and the ISS Excellent Paper Award from the Institute of Electronic, Information and Communication Engineers (IEICE) in 2015 and 2018. He is a member of the ASJ, the IPSJ, the NLP, the IEEE, and the International Speech Communication Association (ISCA).

Invited Talk: Algorithm-Architecture Co-design for 4K HDR Video Applications in IC Design Industry

Abstract: Exploring the concept of algorithm/architecture co-design within the IC design industry, this presentation focuses on early algorithmic complexity analysis and joint optimization. Leveraging data flow and transaction level modeling, high bandwidth and IC area cost issues in 4K video applications are tackled. Through vertical integration of algorithms and architecture, this methodology enhances video application performance and cost-effectiveness, exemplifying its effective approach to real-world challenges.

Speaker:Dr. He Yuan Lin

Senior Technical Manager, Platform System Architecture Div., Intelligent Software Development FU, MediaTek

He-Yuan Lin received his BSEE and PhD EE degrees from National Cheng Kung University. He has several years of research and development experience in IC design. His research spans algorithm/architecture co-design for visual processing. He currently serves as a senior technical manager in MediaTek’s TV team, responsible for optimizing video codec development and related applications. MediaTek TV SoC business holds the world’s highest market share and is recognized as a leading player in the industry.

Registration

• Free for APSIPA / IEEE members
• Non-members